The '819 patent discloses a converter (shown in FIG. 1) which eliminates energy losses during switching. The converter uses semi-conductor power components having controlled blocking, which, in the '819 patent, are designated as "power transistors". A more suitable term for these components, which is used hereinafter, is "controlled blocking static interrupters". This designation encompasses all components which meet the following description: (1) a static electronic component having a control electrode (base, trigger grid . . . ) which hereinafter will be designated as "base" (in order to simplify the terminology and by reference to the designation used in the transistors); (2) a power electrode (emitter, source, cathode . . . ), hereinafter designated as "emitter"; and (3) a second power electrode (collector, drain, anode . . . ), hereinafter designated as "collector". Such a static electronic component has two states: a forwardly biased conduction state characterized by a low voltage drop between the collector and the emitter (V.sub.CE), and a reverse biased blocked state characterized by a low leakage current between emitter and collector. The change of state is under the control of the base electrode, which forwardly or reversely biases the component in accordance with the polarity of signal applied to the component.
Power transistors (bipolar or MOS) meet these criteria, but thyristors or other components also meet these criteria. To increase the voltage range in which the apparatus is utilized (without reducing current performance), transistors having a voltage V.sub.CEX greater than that of the voltage V.sub.CEO, are advantageous as is indicated in the above-mentioned '819 patent. The voltage V.sub.CEX is defined as the voltage of the transistor at no collector current when the base is reverse biased, while the voltage V.sub.CEO is defined as the collector emitter voltage with the base open.
The converter used with the present invention is shown in detail in FIG. 1 of the '819 patent. It comprises at least one power stage provided with two controlled blocking static interrupters, each having a collector, a base, and an emitter, and with a commutation circuit for shunting collector current from each static interrupter during blocking commutations thereof. The two static interrupters are arranged in a half-bridge rectifier configuration across the power supply terminals (+E,-E).
A control stage is provided for each static interrupter for generating a control signal of appropriate form for the conversion to be performed. Finally, a single processing stage is provided for each static interrupter. Each stage has one input connected to receive the control signal, another input connected to the power stage to detect the collector-emitter voltage V.sub.CE of the static interrupter, and an output connected to the base of the static interrupter to trigger the commutations thereof.
One of the signal processing stages will forwardly bias the base of the interrupter when the control signal has a value corresponding to placing the interrupter into conduction, and the voltage V.sub.CE on the interrupter is approximately zero. The other signal processing stage will reverse bias the other interrupter in order to block conduction.
In FIG. 1 of the '819 patent, which is hereinafter termed a converter of the type described, power stage 5 is provided with two controlled blocking static interrupters 7, each of which is associated with signal processing stage 4. Control stage 1 delivers a control signal S.sub.c for each static interrupter, the control signal being in the form of a train of pulses that successively produce blocking and unblocking conditions for the static interrupter.
Diode 8 is associated with each static interrupter of the power stage for recuperation of energy and commutation assistance to rapidly reduce the collector current of the static interrupter at the onset of a blocking commutation. This commutation assistance circuit is formed of condenser 9, placed in parallel between the emitter and the collector of the interrupter 7.
According to an embodiment of the converter described in the '819 patent, each intermediate stage 4 may comprise two shaper circuits M.sub.V and M.sub.C. Shaper circuit M.sub.V operates on voltage V.sub.CE and furnishes a signal in one of either two states, one when the voltage V.sub.CE is almost zero, and the other this voltage is different from zero. Shaper circuit M.sub.C operates on the control signal S.sub.C and furnishes a signal in one of either two states, one which places the power transistor into conduction, the other which blocks the control signal. A logic gate connected to the outputs of the two circuits M.sub.C and M.sub.B performs the logic function and with respect to the signals issuing from the shaping circuits so as to furnish a logic commutation signal having two states. An adaptation circuit A is also provided. This circuit is connected to the AND logic gate and to the base of the power transistor for furnishing base current such that conduction of the interrupter is affected for the state ONE which corresponding to the conduction of the static interrupter. The adaptation circuit furnishes a feed current to the base as a function of the signal issuing from the AND logic gate.
The conventional converter apparatus shown in the '819 patent is designated herein by the Greek letter .DELTA.. It has, as shown in FIG. 1 of the '819 patent, four terminals connected to power electrodes of the two static interrupters 7. To simplify the description which follows, the terminal connected to the collector of the first interrupter is designated C.sub.1 ; the terminal connected to the emitter of this first interrupter is designated E.sub.1 ; the terminal connected to the collector of the second interrupter 7 is designated C.sub.2 ; and the terminal connected to the emitter of the second interrupter is designated E.sub.2.
The present invention aims at extending the domain of use of this apparatus to greater voltages which can be considerably higher (in particular greater than the voltage which can be supported by each interrupter at its terminals) while benefitting from the specific advantages of the base converter (suppression or reduction of commutation energy losses; advantageously, exploitation of voltage V.sub.CEX &gt;V.sub.CEO in the case of bipolar transistors).